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SOPHIA ANTIPOLIS SESSIONS

25/10/00

SESSION

PAPER TITLE

AUTHOR(S)
PRESENTER

COMPANY

9H00 Session 1
CODESIGN

Chairman:
Jacques-Olivier Piednoir (Cadence)

 CODEF: A System Level Design Space Exploration Tool M. Auguin, L. Capella,
F. Cuesta, E. Gresset		 I3S/PHILIPS
IP Communication Refinement in Cosy-Vcc Flow JY. Brunel PHILIPS
Memory Optimization of Data Flow Applications at the Codesign Level A. Fraboulet,
L. Just-Meunier,
A. Mignotte		 CADENCE
Software Protocol Stack Development in SDL D. Audoly NEWLOGIC

9H00 Session 2
 SOC

Chairman:
Michel Eftimakis (NewLogic)

 A Standard Communication Platform Y. Nogues PHILIPS
Design and Verification Methodology of Modern High-Speed Switches F. Abel IBM
Design of a single chip 4 Gbps Network Processor F. Verplanken IBM
MicroNetworks for Flexible SOC Platforms D. Wingard SONICS

11H00 KEY NOTE

Paul McLellan (Cadence Corporate VP Strategic Marketing)
"The Future of Design"

13H30 Session 3
 IP CORE

Chairman:
Pierre Bricaud (Mentor Graphics)

 A High Quality Physical Random Number Generator M. Dichtl, N. Janssen SIEMENS/INFINEON Munich
A Portable All Digital Phase-Locked Loop X. Gense, A.V. Malshin, I.A. Esakov,
A.A. Gaydukov,
A.A. Postavnoy		 AVANT!
MCST, Moscow
An IP Core for the Wavelet Transform C. Diou, L. Torres,
M. Robert		 LIRMM
Testing Embedded Synthesizable IP - A Case Study A. Burdass, G.Campbell, R. Grisenthwaite, R.York ARM

16H00 Session 4
 IP CORE

Chairman:
Pierre Bricaud (Mentor Graphics)

 Example of IP reuse integration using web-based-solutions J. Chaix MENTOR Graphics
Optimized Development of Bluetooth Systems M. Eftimakis NEWLOGIC
Unispeech: a Configurable Speech Processor L. Affortunati, F. Basile, O. Boccaccio, C. Daniel, PdeNicola, R. Fortas, J. Lelan, P. Pagano INFINEON

14H00 Session 5
 EDA / FLOW

Chairman:
Laurent Chouraki (Cadence)

 Fast, Thorough, Full-Chip Implementation Verification E. Marschner, N. Khalil, S. Pagey CADENCE
Software modelling of a DSP-based architecture using Esterel and UML methodologies to improve validation and enable formal verification L. Leblanc, L. Arditi,
G. Clave		 TEXAS INSTRUMENTS
RFIC Design with verification at System Level on 3G UMTS Dircet conversion receiver J. Hartung, J.E. Chen,
R. Wittmann, U. Seeling, P. Schwarz		 CADENCE, NOKIA, ATMEL, FRAUNHOFER INSTITUT

16H00 Session 6
 EDA / FLOW

Chairman:
Andr� Kuntz (Philips)

 Clock Tree: The Quest for Zero Skew is Over T. Sarrazin CADENCE
In-Place Timing Optimization J. Koehl, J. Schietke IBM/Bonn University
Power Optimisation for DSP J. Laurent, N. Julien,
E. Martin		 LESTER

AIX en PROVENCE SESSIONS

26/10/00

SESSION

PAPER TITLE

AUTHOR(S)
PRESENTER

COMPANY

10H00 Session 7
 OPC / PSM

Chairman:
Arnold Ginetti (Cadence)

PANEL 10mn PRESENTATION
An OPC Mask Friendly Approach or How to take into accounts Mask Manufacturing Limitations O. Toublan, P. Leclaire
C. West, G. Galan		 MENTOR Graphics
DuPont Photomasks
Lithography Compliance: Design for PSM/OPC-Friendly Layouts M. Rieger, J. Mayhew AVANT! (US)
Optical Proximity Correction L. Thenie CADENCE
PSM: a Sequence of Graph Problems M. Sanie NUMERICAL Technologies

10H00 Session 8
 PROCESS

Chairman:
Bruno Delepine (Philips)

 Mask Manufacturing Contribution on 248nm&193nm Lithography Performances A. Barberet,
JC Richoilley, M. Tissier, G. Fanget, Y. Quere		 DuPont Photomasks
CEA/LETI
MEMS Micro-Switches in RF Designs X. Lafontan,
F. Pressecq, C. Dufaza, M. Robert		 CNES
LIRMM
Process Simulation & Modeling M. Sanie NUMERICAL Technologies
Use of Semiconductor Mechanical Interface SMIF in wafer Probing (Electrical Wafer Test) E. Ferradino STMicroelectronics

13H00 Session 9
 TEST

Chairman:
Yves Bertrand (LIRMM)

 Partial Reset Techniques for 100% Fault Coverage A. Petitqueux,
ML.Flottes, C. Landrault		 LIRMM
Wrapper Design for Embedded Core Test EJ. Marinissen, M.Lousberg, S. Goel
L. Souef		 PHILIPS

10H00 Session 10
 TIMING EMC

Chairman:
Robert Ronchi (STMicroelectronics)

 EMC Conception Method of High Density Integrated Circuit JL. Levant, M. Ramdani TEMIC-MHS/ESEO
Reduction of Electromagnetic Emissions in Arithmetic Circuits through Clock Skew Optimisation F. Gregoretti,
C. Passerone, L.Reyneri,
F. Fiori, I. Blunno		 Politecnico di Torino
Simulation and Measurements of Electromagnetic Radiations Produced by Integrated Circuits JY. Oberl�, JC. Perrin TEXAS INSTRUMENTS

14H00 Session 11
 INTERCONNECT

Chairman:
Laurent Thenie (Cadence)

 Evolution of Interconnect (presentation of the session on Interconnect)
Accurate and Efficient On-Chip Copper Interconnect Modeling Including Cladding Metal LF. Chang, KJ Chang, R. Mathews SEQUENCE DESIGN
Crosstalk Evaluation in Totally and Partially Coupling G. Servel, D. Deschacht LIRMM